Comparative Performance Analysis of BLDC Motor Speed Control Using CPLD-Based Implementation

Abstract

The widespread usage of brushless motors in today's technological trend necessitates the occasional development of novel control techniques. This study compares the mathematical design of speed control for a brushless direct current (BLDC) motor using a complex programmable logic device (CPLD) with the implementation of speed control without CPLD modeling. A PWM technique is used to mathematically construct speed control by applying different duty cycles to a 3-ф inverter. The rotor position is determined via Hall sensors, which act as references to synchronize the PWM control signals. Verilog Hardware Description Language (VHDL) is used to write the control model, which is then validated by simulation of with CPLD. To evaluate the BLDC motor's speed performance under PWM control, an experimental setup is constructed. A 500W BLDC motor with a 48V rating is equipped with CPLD Max II devices to implement the control algorithm. This system generates PWM with a configurable duty cycle for a working frequency of roughly 20 kHz and commutates consecutively up to 400 RPM using a six-step commutation.